1. Field of the Invention
This invention relates to circuitry for a digital data processing system and more particularly to an apparatus for providing a specified binary sequence termed a mask.
2. Description of the Related Art Including Information Disclosed under 37 CFR 1-97-1.99
A mask is a predefined binary sequence. A mask is used to extract specific bits from a data word or another data sequence while suppressing other bits in the word or sequence. An example of a mask would be a binary sequence containing a series of 1's surrounded by 0's. When this mask is ANDed with some other data word, the data in this other data word at the bit locations of the 1's in the mask word will be exposed. The bits and the data word at the locations corresponding to the 0 bit locations in the mask word will be suppressed.
This invention provides a mask generation unit that specifies a mask of 1's surrounded by 0's or 0's surrounded by 1's.
U.S. Pat. No. 4,087,811 entitled "Threshold Decoder", discloses a type of mask generator designed with the purpose of minimizing the total number of gates. However, using the technique of this patent, a considerable amount of wiring is required.
U.S. Pat. No. 4,569,016 entitled "Mechanism For Implementing One Machine Cycle Executable Mask and Rotate Instructions In A Primitive Instruction Set Computing System" discloses a circuit for performing full shift, merge, insert and bit alignment functions within a single machine operating cycle. However, this patent does not disclose the specific circuitry embodiment of the mask generation unit. This patent does, however, discuss the importance of the execution of an instruction in a single machine operating cycle. The present invention is intended to perform the mask generation function within a single machine cycle operation.
IBM Technical Disclosure Bulletin, Vol. 24, No. 10A, March 1985, pages 5696-5698, entitled "Mask Generator for 32 Bit Microprocessors" discloses mask generation using an eleven bit instruction.
IBM Technical Disclosure Bulletin, Vol. 26, No. 1, June 1983, pages 197-198, entitled "Four-Bit Look-Ahead Mask Generator", discloses a look-ahead mask generator that provides improved access time.
IBM Technical Disclosure Bulletin, Vol. 23, No. 1, June 1980, pages 149-150, entitled "Mask Generator", discloses a mask generating circuit using a bit shifter.
It is an object of the present invention to provide a mask generation unit that minimizes the layout of circuitry in a field effect transistor environment.